1. Field of the Invention
The present invention is related to a flash storage device, and more particular to a flash storage device that is able to correct data when performing copy back instruction and operation on the flash memory.
2. Description of Related Art
In recent years, since NAND flash provides advantages of low production cost, fast read/write speed, reduced energy consumption, and high reliability, it has been widely applied in consumer electronic products for use in storage media.
Due to the fact that the operations for unit capacity read/write and unit capacity erase in NAND flash are essentially different, therefore a special approach (generally referred as Flash File System (FFS)) is required to allocate and manage the storage space in NAND flash. Herein the unit capacity read/write uses “page”, while the unit capacity erase is based on “block”; also, block are bigger in capacity, usually consisting of 32 or 64 pages. Additionally, upon data update, NAND flash needs to be erased before being written in new data; hence, when only part of the data within a block needs to be simultaneously updated, it is necessary to copy the remaining part of the data that is not undergoing update and still valid, so as to move the valid data onto a erased block.
In order to increase the speed of copying data from a source memory block to a target memory block in NAND flash, NAND flash will provide new instructions and communication protocols, thereby allowing the data originally recorded in a memory unit in NAND flash to be first read (i.e. retrieved) into a page buffer in NAND flash, therefore without transferring the data to controllers located outside NAND flash, it is possible to send the data back to other positions of memory unit in NAND flash. That is, it is possible to first execute the Read Page instruction, then the Write Page instruction (commonly referred as the Program instruction), so as to directly record the data held in the page buffer back to other positions of memory units in NAND flash, and each time a page of data can be directly copied. Therein, such instructions and communication protocols are known as Copy Back instruction and operation.
Due to limited reliability on data retention of the memory units in NAND flash, NAND flash manufacturers usually propose a recommended strength regarding the adopted Error Correction Code (ECC) in their specifications. For example, if the suggested ECC strength is 1 bit/512 Byte, then it indicates that if an error occurs in one (1) bit out of 512 bytes of data, it can be detected and corrected.
It should be noted that under certain conditions a problem might occur, such as when a controller performs copy back operation on NAND flash. Since the data recorded in the memory unit is not transferred outside of the NAND flash, i.e. error check is not performed by the controller; then as a result, suppose an error does occur in the data originally recorded in NAND flash and that the data is copied to other positions through the copy back instruction, so now erroneous data will be copied directly from the source page to the new target page, without going through the error detection and correction procedure.
In order to overcome this problem, prior art technology has proposed that after the completion of copy back operation, the controller furthermore reads the data already copied in the new target page through the read page instruction, so as to perform ECC check and verify the correctiveness of such data. Also, in case the occurrence of data error is detected, then abandon the copied data and execute correction process.
However, although this well-known prior art practice can locate errors in data and then perform the necessary corrections after the completion of copy back operation, but because the data has been copied from the source page to the target page, so that the erroneous data now occupies the target page. Therefore, the prior art requires copying all the valid data in the target page again to move the valid data onto other blocks, and erase the target block that holds the erroneous data. As a result, when data errors did occur, there will be extra time delays and correction operations, which will seriously affect the effect and objective of using copy back process to improve the speed for data write and update.
To resolve this issue, the industry has currently proposed a new controller operation mode, so that during the operation of copy back, after reading the data in the memory unit of NAND flash and placing it into the page buffer in NAND flash, the controller may first read the data located in the page buffer then check its correctiveness; and when an error is detected, it performs correction operations on the erroneous data in the page buffer, and then “programs” (i.e. copy) the corrected data to a new position in the memory unit.
However, even though the aforementioned prior art operation process can correct the errors within the source data, ensures that the copy back operation can program the correct data to the new position; but when the prior art operation process finds errors and corrects them, it is required to detect the positions where data errors occur by the controller via ECC check code, and correct these errors one by one. The positions where the errors occur are not necessarily continuous, so it needs to complete the corrections of data errors in the page buffer by inputting instruction, data address, and correct data in a one-by-one approach. Therefore, in a situation where data errors are many, the prior art operation process needs significantly so much process time, that the objective of operation time reduction can not be achieved effectively.